The present invention relates to manufacturing methods of semiconductor devices, and more specifically, to a technique suitably applied to a manufacturing method of a semiconductor device having a metal-insulator-semiconductor field-effect transistor (MISFET).
A MISFET can be fabricated by forming a gate insulating film over a semiconductor substrate, forming a gate electrode over the gate insulating film, and then forming source and drain regions by ion implantation or the like. After forming the MISFET, an interlayer insulating film is formed over the semiconductor substrate to cover the MISFET, contact holes are formed in the interlayer insulating film, conductive plugs are formed to fill in the contact holes, and then wirings are formed, which can produce a semiconductor device having the MISFET.
Japanese Unexamined Patent Publication No. 2000-236090 (Patent Document 1), and Japanese Unexamined Patent Publication No. 2010-40734 (Patent Document 2) disclose techniques that involve forming source and drain regions by implantation of impurities using sidewalls as a mask and then etching the sidewalls.